Jing Tian (田静)

南京大学集成电路学院 助理教授 博士生导师

Assistant Professor, Ph.D. Advisor

Nanjing University, Suzhou Campus
Nanjing University

Email: tianjing@nju.edu.cn

Office: Room C304, Kechuang Building, Nanjing University, Suzhou Campus

目前拟招收2025级博士生和硕士生，请感兴趣的同学发送简历至我邮箱。
Short Bio
I am currently an Assistant Professor at the School of Integrated Circuits, Nanjing Univerxity (NJU), where I direct the Intelligence and Cryptography IC Design (IC2) Lab. Prior to that, I was an Associate Researcher with Nanjing University from 2020 to 2023. I received the B.S. degree in microelectronics and the Ph.D. degree in information and communication engineering from Nanjing University, Nanjing, China, in 2015 and 2020, respectively. I was supervised by Prof. Zhongfeng Wang, the Fellow of IEEE. My research interests include VLSI design for cryptographic engineering, artificial intelligence, and side channel attack and defense.
Teaching
Professional Services
Honors and Awards
Research Group
Graduate Students Research Assistants
Publications
  1. [TCAS-II 2025] A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber
    D. Xu, K. Wang and J. Tian,
    in IEEE Transactions on Circuits and Systems II: Express Briefs , 2025.
  2. [TCAS-I 2025] Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece
    H. Zhang, X. Qiao, J. Tian, S. Song and Z. Wang,
    in IEEE Transactions on Circuits and Systems I: Regular Papers , 2025.
  3. [AES 2024] 一种应用于BIKE的基于Karatsuba算法的大尺寸多项式乘法器
    杨柳, 张永真, 田静, 宋苏文, 王中风,
    in 电子学报(Acta Electronica Sinica) , 2024.
  4. [APCCAS 2024] LEAM: A Low-Area and Efficient Accelerator of Matrix-Vector Multiplication for Homomorphic Encryption
    Z. Cui and J. Tian,
    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2024.
  5. [TCAS-I 2024] HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers
    X. Zhang, Y. Wei, M. Li, J. Tian and Z. Wang,
    in IEEE Transactions on Circuits and Systems I: Regular Papers , 2024.
  6. [SOCC 2023] An Efficient Hardware Design for Fast Implementation of HQC
    C. Li, S. Song, J. Tian, Z. Wang and Ç. K. Koç,
    in IEEE 36th International System-on-Chip Conference , 2023.
  7. [TCAD 2023] Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber
    M. Li, J. Tian, X. Hu and Z. Wang,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2023.
  8. [ISCAS 2023] Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications
    H. Xiong, B. Xiong, W. Wang, J. Tian, H. Zhu and Z. Wang,
    in IEEE International Symposium on Circuits and Systems , 2023.
  9. [ISQED 2023] Efficient Decryption Architecture for Classic McEliece
    X. Qiao, S. Song, J. Tian and Z. Wang,
    in the 24th International Symposium on Quality Electronic Design , 2023.
  10. [ISQED 2023] High-Throughput Hardware Implementation for Haraka in SPHINCS+
    Y. Dai, Y. Song, J. Tian and Z. Wang,
    in the 24th International Symposium on Quality Electronic Design , 2023.
  11. [TCAS-II 2023] Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation
    L. Ou, D. Zhu, J. Tian and Z. Wang,
    in IEEE Transactions on Circuits and Systems II: Express Briefs , 2023.
  12. [TCHES 2023] Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation
    D. Zhu, R. Zhang, L. Ou, J. Tian and Z. Wang,
    in IACR Transactions on Cryptographic Hardware and Embedded Systems , 2023.
  13. [APCCAS 2022] High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber
    M. Li, J. Tian, X. Hu, Y. Cao and Z. Wang,
    in IEEE Asia Pacific Conference on Circuits and Systems , 2022.
  14. [TCAS-I 2022] AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography
    X. Hu, J. Tian, M. Li and Z. Wang,
    in IEEE Transactions on Circuits and Systems I: Regular Papers , 2022.
  15. [TC 2022] Low-latency Hardware Architecture for VDF Evaluation in Class Groups
    D. Zhu, J. Tian, M. Li and Z. Wang,
    in IEEE Transactions on Computers , 2022.
  16. [TCAS-I 2022] A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature
    Y. Song, X. Hu, J. Tian and Z. Wang,
    in IEEE Transactions on Circuits and Systems I: Regular Papers , 2022.
  17. [WAIFI 2022] Reduction-Free Multiplication for Finite Fields and Polynomial Rings
    SC Oliva Madrigal, G Saldamlı, C Li, Y Geng, J. Tian, Z Wang and ÇK Koç,
    in International Workshop on the Arithmetic of Finite Fields , 2022.
  18. [VLSI 2022] Efficient Homomorphic Convolution Designs on FPGA for Secure Inference
    X. Hu, M. Li, J. Tian and Z. Wang,
    in IEEE Transactions on Very Large Scale Integration , 2022.
  19. [ISVLSI 2022] An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking
    L. Yang, J. Tian, B. Wu, Z. Wang and H. Ren,
    in IEEE Computer Society Annual Symposium on VLSI , 2022.
  20. [ISCAS 2022] A High-Speed Codec Architecture for Lagrange Coded Computing
    B. Xiong, J. Tian and Z. Wang,
    in IEEE International Symposium on Circuits and Systems , 2022.
  21. [JCS 2021] 基于FPGA的Leighton-Micali签名方案密钥生成的高速可配置实现
    胡潇, 宋逸峰, 汪文浩, 田静,
    in 信息安全学报 (Journal of Cyber Security) , 2021.
  22. [TCAS-I 2021] High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier
    J. Tian, B. Wu and Z. Wang,
    in IEEE Transactions on Circuits and Systems I: Regular Papers , 2021.
  23. [ASAP 2021] DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography
    X. Hu, M. Li, J. Tian and Z. Wang,
    in IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors , 2021.
  24. [ISCAS 2021] High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol
    Y. Song, X. Hu, W. Wang, J. Tian and Z. Wang,
    in IEEE International Symposium on Circuits and Systems , 2021.
  25. [ISCAS 2021] Low-latency architecture for the parallel extended GCD algorithm of large numbers
    D Zhu, J Tian, Z Wang,
    in IEEE International Symposium on Circuits and Systems , 2021.
  26. [TC 2021] Efficient software implementation of the SIKE protocol using a new data representation
    J Tian, P Wang, Z Liu, J Lin, Z Wang, J Großschädl,
    in IEEE Transactions on Computers , 2021.
  27. [CL 2021] An improved reliability-based decoding algorithm for NB-LDPC codes
    S Song, J Tian, J Lin, Z Wang,
    in IEEE Communications Letters , 2021.
  28. [APCCAS 2020] Fast permutation architecture on encrypted data for secure neural network inference
    X Hu, J Tian, Z Wang,
    in IEEE Asia Pacific Conference on Circuits and Systems , 2020.
  29. [APCCAS 2020] An efficient accelerator of the squaring for the verifiable delay function over a class group
    D Zhu, Y Song, J Tian, Z Wang,
    in IEEE Asia Pacific Conference on Circuits and Systems , 2020.
  30. [SOCC 2020] A high-speed architecture for the reduction in VDF based on a class group
    Y Song, D Zhu, J Tian, Z Wang,
    in IEEE 33rd International System-on-Chip Conference , 2020.
  31. [TVLSI 2020] Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography
    J Tian, J Lin, Z Wang,
    in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2020.
  32. [ISVLSI 2020] A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography
    B Wu, J Tian, X Hu, Z Wang,
    in IEEE Computer Society Annual Symposium on VLSI , 2020.
  33. [ASICON 2019] Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes
    S Song, J Tian, J Lin, Z Wang,
    in IEEE 13th International Conference on ASIC , 2019.
  34. [TCAS-II 2019] A novel iterative reliability-based majority-logic decoder for NB-LDPC codes
    S Song, H Cui, J Tian, J Lin, Z Wang,
    in IEEE Transactions on Circuits and Systems II: Express Briefs , 2019.
  35. [ISCAS 2019] A novel low-complexity joint coding and decoding algorithm for NB-LDPC codes
    S Song, J Tian, J Lin, Z Wang,
    in IEEE International Symposium on Circuits and Systems , 2019.
  36. [TCAS-II 2019] Optimized trellis-based min-max decoder for NB-LDPC codes
    J Tian, S Song, J Lin, Z Wang,
    in IEEE Transactions on Circuits and Systems II: Express Briefs , 2019.
  37. [SiPS 2019] Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography
    J Tian, J Lin, Z Wang,
    in IEEE International Workshop on Signal Processing Systems , 2019.
  38. [CL 2019] Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders
    W Li, J Tian, J Lin, Z Wang,
    in IEEE Communications Letters , 2019.
  39. [Access 2019] Efficient T-EMS Based Algorithms for High-Order LDPC Codes
    J Tian, S Song, J Lin, Z Wang,
    in IEEE Access , 2019.
  40. [APCCAS 2018] Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding
    J Tian, J Lin, Z Wang,
    in IEEE Asia Pacific Conference on Circuits and Systems , 2018.
  41. [ISCAS 2018] An efficient NB-LDPC decoding algorithm for next-generation memories
    J Tian, J Lin, Z Wang,
    in IEEE International Symposium on Circuits and Systems , 2018.
  42. [ICCT 2017] A reduced complexity decoding algorithm for NB-LDPC codes
    S Song, J Lin, J Tian, Z Wang,
    in IEEE 17th International Conference on Communication Technology , 2017.
  43. [TCAS-II 2017] A 21.66 Gbps nonbinary LDPC decoder for high-speed communications
    J Tian, J Lin, Z Wang,
    in IEEE Transactions on Circuits and Systems II: Express Briefs, 2017.
Last updated on Jan., 2025 by Jing.